36 lines
601 B
Systemverilog
36 lines
601 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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interface ifc;
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integer ok;
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integer bad;
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modport out_modport(output ok);
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endinterface
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module t;
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integer cyc = 1;
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ifc itop ();
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counter_ansi c1 (
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.isub(itop),
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.i_value(4'h4)
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);
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endmodule
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module counter_ansi (
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ifc.out_modport isub,
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input logic [3:0] i_value
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);
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always @* begin
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isub.ok = i_value;
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isub.bad = i_value; // Illegal access
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end
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endmodule
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