32 lines
492 B
Systemverilog
32 lines
492 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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Pub pub ();
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localparam ZERO = 0;
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if (ZERO) Dead dead ();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module Pub;
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// verilator public_module
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// no signals here
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endmodule
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module Dead;
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// verilator public_module
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endmodule
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