41 lines
877 B
Systemverilog
41 lines
877 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkf(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%0f exp=%0f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module sub_a (
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input real i1[1:2]
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);
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endmodule
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module sub_b (
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input real i2[2:1]
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);
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sub_a sub_a (.i1(i2));
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endmodule
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module t;
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real i2[2:1];
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sub_b sub_b (.i2);
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initial begin
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i2[2] = 2.22;
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i2[1] = 1.11;
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#1;
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`checkf(i2[2], 2.22);
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`checkf(i2[1], 1.11);
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`checkf(sub_b.i2[2], 2.22);
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`checkf(sub_b.i2[1], 1.11);
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`checkf(sub_b.sub_a.i1[2], 1.11);
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`checkf(sub_b.sub_a.i1[1], 2.22);
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end
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endmodule
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