46 lines
1.0 KiB
Systemverilog
46 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Anthony Donlon
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// SPDX-License-Identifier: CC0-1.0
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module sub ();
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endmodule
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interface axi_stream_if #(
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parameter int DATA_WIDTH = 64,
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parameter type TUSER_TYPE = logic
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) (
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input clk
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);
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task mytask();
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endtask : mytask
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genvar my_genvar;
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logic tvalid;
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sub i_sub ();
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localparam PACKED_DATA_WIDTH = DATA_WIDTH + DATA_WIDTH / 8 + 1 + $bits(TUSER_TYPE);
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endinterface
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module t;
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logic clk;
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// overriding a localparam
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axi_stream_if #(.PACKED_DATA_WIDTH(10)) axis1 (clk);
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// overriding a non-var
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axi_stream_if #(.mytask(10)) axis2 (clk);
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// overriding a non-port/interface/param var
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axi_stream_if #(.my_genvar(10)) axis3 (clk);
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// overriding a port
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axi_stream_if #(.clk(10)) axis4 (clk);
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// overriding a signal
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axi_stream_if #(.tvalid(10)) axis5 (clk);
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// overriding an instance
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axi_stream_if #(.i_sub(10)) axis6 (clk);
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endmodule
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