49 lines
1.3 KiB
Systemverilog
49 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2024 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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function string validate_time_precision(string precision);
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static string valid_precision[$] = '{"ps", "ns", "us", "ms", "s"};
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if (!(precision inside {valid_precision})) begin
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return "none";
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end
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return precision;
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endfunction
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initial begin
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automatic int q[$] = {1, 2};
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string s;
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if (!(1 inside {q[0], q[1]})) $stop;
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if (3 inside {q[0], q[1]}) $stop;
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s = validate_time_precision("ps");
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`checks(s, "ps");
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s = validate_time_precision("ns");
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`checks(s, "ns");
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s = validate_time_precision("us");
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`checks(s, "us");
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s = validate_time_precision("ms");
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`checks(s, "ms");
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s = validate_time_precision("s");
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`checks(s, "s");
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s = validate_time_precision("random");
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`checks(s, "none");
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s = validate_time_precision("");
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`checks(s, "none");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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