38 lines
737 B
Systemverilog
38 lines
737 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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// Test if temporary vars are relinked if not used directly under FTASK.
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package A; // Create JUMPBLOCK; use n++ in it
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task t;
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automatic int n;
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if ($random) return;
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n = n++;
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endtask
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endpackage
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package B; // Create IF; use n++ in it
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int n;
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task t;
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if ($random) n = n++;
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endtask
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endpackage
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module C; // Like above but in a module
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int n = 0;
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initial if ($random) n = n++;
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endmodule
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module t; // Actually use those to test relinking
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C c ();
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initial begin
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A::t();
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B::t();
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end
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endmodule
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