39 lines
632 B
Systemverilog
39 lines
632 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Wilson Snyder
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// SPDX-License-Identifier: Unlicense
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module flop (
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q,
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d,
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clk
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);
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// No AUTOARG; order of below is different from port order above
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input wire clk;
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output reg q;
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input wire d;
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// verilator hier_block
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always_ff @(posedge clk) begin
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q <= d;
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end
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endmodule
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module t (
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output wire q,
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input wire d,
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input wire clk
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);
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// This intentionally uses pin number ordering
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flop u_flop (
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q,
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d,
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clk
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);
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endmodule
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