35 lines
713 B
Systemverilog
35 lines
713 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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generate
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for (genvar i = 0; i < 2; ++i) Core hierCore (clk);
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endgenerate
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always @(negedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module Core (
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input clk
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); /* verilator hier_block */
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generate
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for (genvar i = 0; i < 2; ++i) SubCore sub (clk);
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endgenerate
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always @(posedge clk) $display("%m");
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endmodule
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module SubCore (
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input clk
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); /* verilator hier_block */
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always @(posedge clk) $display("%m");
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endmodule
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