56 lines
1.1 KiB
Systemverilog
56 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t (
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input clk
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);
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byte out1;
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shortint out2;
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int out3;
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longint out4;
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integer out5;
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time out6;
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sub sub (
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out1,
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out2,
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out3,
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out4,
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out5,
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out6
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);
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always_ff @(posedge clk) begin
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if (out1 == 1 && out2 == 2 && out3 == 3 && out4 == 4 && out5 == 5 && out6 == 6) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$write("Mismatch\n");
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$stop;
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end
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end
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endmodule
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module sub (
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output byte out1,
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output shortint out2,
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output int out3,
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output longint out4,
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output integer out5,
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output time out6
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); /*verilator hier_block*/
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assign out1 = 1;
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assign out2 = 2;
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assign out3 = 3;
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assign out4 = 4;
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assign out5 = 5;
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assign out6 = 6;
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endmodule
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