30 lines
693 B
Systemverilog
30 lines
693 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2024 Antmicro
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t (
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input clk
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);
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bit [31:0] outA;
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bit [31:0] outB;
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subA subA (.out(outA));
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subB subB (.out(outB));
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always @(posedge clk) begin
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if (outA == `VALUE_A && outB == `VALUE_B) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$write("Mismatch\n");
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$stop;
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end
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end
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endmodule
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