25 lines
615 B
Systemverilog
25 lines
615 B
Systemverilog
// DESCRIPTION: Verilator: Demonstrate deferred linking across module
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// bondaries
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2015 Todd Strader
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// SPDX-License-Identifier: CC0-1.0
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module m1 ();
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logic v1;
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endmodule
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module t;
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for (genvar the_genvar = 0; the_genvar < 4; the_genvar++) begin : m1_b
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m1 m1_inst ();
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end
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for (genvar the_other_genvar = 0; the_other_genvar < 4; the_other_genvar++) begin
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always_comb m1_b[the_other_genvar].m1_inst.v1 = 1'b0;
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end
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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