14 lines
336 B
Systemverilog
14 lines
336 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2005 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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integer i;
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generate
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for (i = 0; i < 3; i = i + 1) begin // Bad: i is not a genvar
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end
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endgenerate
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endmodule
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