45 lines
1.3 KiB
Systemverilog
45 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// simplistic example, should choose 1st conditional generate and assign straight through
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// the tool also compiles the special case and determines an error (replication value is 0)
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2008 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns / 1ps
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module t (
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data_i,
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data_o,
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single
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);
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parameter OP_BITS = 32;
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input [OP_BITS -1:0] data_i;
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output [31:0] data_o;
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input single;
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// Bare begin/end extension of IEEE allowed by most all tools
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begin
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end
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begin : named
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end : named
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//simplistic example, should choose 1st conditional generate and assign straight through
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//the tool also compiles the special case and determines an error (replication value is 0
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generate
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if (OP_BITS == 32) begin : general_case
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assign data_o = data_i;
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// Test implicit signals
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/* verilator lint_off IMPLICIT */
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assign imp = single;
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/* verilator lint_on IMPLICIT */
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end
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else begin : special_case
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assign data_o = {{(32 - OP_BITS) {1'b0}}, data_i};
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/* verilator lint_off IMPLICIT */
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assign imp = single;
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/* verilator lint_on IMPLICIT */
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end
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endgenerate
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endmodule
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