141 lines
2.5 KiB
Systemverilog
141 lines
2.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2007 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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wire [3:0] Value = crc[3:0];
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wire [3:0] Result;
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wire [3:0] Result2;
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Testit testit ( /*AUTOINST*/
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// Outputs
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.Result(Result[3:0]),
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.Result2(Result2[3:0]),
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// Inputs
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.clk(clk),
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.Value(Value[3:0])
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);
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x %x %x\n", $time, cyc, crc, Result, Result2);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= {56'h0, Result, Result2} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc < 10) begin
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sum <= 64'h0;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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if (sum !== 64'h4af37965592f64f9) $stop;
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$finish;
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end
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end
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endmodule
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module Test (
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clk,
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Value,
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Result
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);
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input clk;
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input Value;
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output Result;
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reg Internal;
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assign Result = Internal;
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always @(posedge clk) Internal <= Value;
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endmodule
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module Test_wrap1 (
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clk,
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Value,
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Result
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);
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input clk;
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input Value;
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output Result;
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Test t (
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clk,
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Value,
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Result
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);
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endmodule
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module Test_wrap2 (
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clk,
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Value,
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Result
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);
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input clk;
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input Value;
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output Result;
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Test t (
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clk,
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Value,
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Result
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);
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endmodule
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module Testit (
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clk,
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Value,
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Result,
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Result2
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);
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input clk;
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input [3:0] Value;
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output [3:0] Result;
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output [3:0] Result2;
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genvar i;
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generate
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for (i = 0; i < 4; i = i + 1) begin : a
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if ((i == 0) || (i == 2)) begin : gblk
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Test_wrap1 test (
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clk,
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Value[i],
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Result[i]
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);
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end
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else begin : gblk
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Test_wrap2 test (
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clk,
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Value[i],
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Result[i]
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);
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end
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end
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endgenerate
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assign Result2[0] = a[0].gblk.test.t.Internal;
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assign Result2[1] = a[1].gblk.test.t.Internal;
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assign Result2[2] = a[2].gblk.test.t.Internal;
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assign Result2[3] = a[3].gblk.test.t.Internal;
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endmodule
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