18 lines
348 B
Systemverilog
18 lines
348 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2024 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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parameter X = 2;
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begin : block
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end
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begin : block
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end
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if (X > 0) begin : block1
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end
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if (X > 1) begin : block1
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end
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endmodule
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