21 lines
574 B
Systemverilog
21 lines
574 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module bug_reduction_nor_binary (
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input logic [3:0] var1,
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input logic [3:0] var2,
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output logic [3:0] out1,
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output logic [3:0] out2
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);
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assign out1 = var1~|var2; //< ~| is a unary reduction operator, not a binary infix operator
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assign out2 = var1~&var2; //< ~& is a unary reduction operator, not a binary infix operator
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// ~^ is legal
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endmodule
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