21 lines
352 B
Systemverilog
21 lines
352 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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function static int func();
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int cnt = 0;
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return ++cnt;
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endfunction
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module t;
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int a;
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initial begin
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a = func;
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$stop;
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end
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endmodule
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