28 lines
988 B
Systemverilog
28 lines
988 B
Systemverilog
// DESCRIPTION: Test for IEEE 1800-2023 6.22.2 - 4-state to 2-state type equivalence
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// This should produce a type error because bit and logic are not equivalent types
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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// IEEE 6.22.2: Packed arrays are equivalent if they contain the same number
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// of total bits, are either all 2-state or all 4-state, and are either all
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// signed or all unsigned.
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// 2-state array
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bit [7:0] arr_2state[3:0];
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// 4-state array (should not be assignment compatible for unpacked arrays)
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logic [7:0] arr_4state[3:0];
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initial begin
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// Per IEEE 7.6: For unpacked arrays to be assignment compatible,
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// the element types shall be equivalent.
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// bit[7:0] and logic[7:0] are NOT equivalent (one is 2-state, one is 4-state)
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arr_2state = arr_4state;
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$write("*-* All Coverage *-*\n");
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$stop;
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end
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endmodule
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