43 lines
1.2 KiB
Systemverilog
43 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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reg [63:0] sum; // Checked not in objects
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reg [2:1][4:3] array[5:6][7:8];
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bit [3:2][2:1] array2[5:4][2];
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string did;
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initial begin
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sum = 0;
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foreach (array[]) begin // NOP
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++sum;
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end
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`checkh(sum, 0);
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sum = 0;
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foreach (array[,,]) begin // NOP
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++sum;
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end
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`checkh(sum, 0);
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foreach (array2[i, j,, l]) begin
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did = {did, $sformatf("; %0d,%0d,,%0d", i, j, l)};
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end
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`checks(did, "; 5,0,,2; 5,0,,1; 5,1,,2; 5,1,,1; 4,0,,2; 4,0,,1; 4,1,,2; 4,1,,1");
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$finish;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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