33 lines
726 B
Systemverilog
33 lines
726 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2022 Pawel Jewstafjew <Pawel.Jewstafjew@gmail.com>
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// SPDX-License-Identifier: CC0-1.0
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interface Iface (
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input bit [31:0] regs[1]
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);
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initial begin
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automatic string instance_path = $sformatf("%m");
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$display("Iface path %s\n", instance_path);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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bit [0:0] ppp;
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always_comb begin
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// Ok:
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//for (int index = 1 ; index < 2 ; ++index) begin
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foreach (regs[index]) begin
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ppp[index] = 1;
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end
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end
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endinterface
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module top (
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input bit [31:0] regs[1]
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);
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Iface t1 (.regs(regs));
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endmodule
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