24 lines
504 B
Systemverilog
24 lines
504 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Eunseo Song
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// SPDX-License-Identifier: CC0-1.0
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module top (
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input clk,
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input rst,
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output reg [7:0] count
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);
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always @(posedge clk) begin
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if (rst) count <= 0;
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else count <= count + 1;
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end
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initial begin
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$display("Hello from t_flag_csplit_pch");
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$write("*-* All Coverage-Coverage = 1\n");
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$finish;
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end
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endmodule
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