33 lines
551 B
Systemverilog
33 lines
551 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2014 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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//`begin_keywords "VAMS-2.3"
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`begin_keywords "1800+VAMS"
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module t ( /*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in
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);
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input in;
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wreal in;
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output out;
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wreal out;
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import "DPI-C" context function void dpii_call(
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input real in,
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output real out
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);
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initial begin
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dpii_call(in, out);
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$finish;
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end
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endmodule
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