32 lines
620 B
Systemverilog
32 lines
620 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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sub_0 sub_0 (clk);
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sub_1 sub_1 (clk);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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import "DPI-C" context function void dpii_call();
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module sub_0 (
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input clk
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); /*verilator hier_block*/
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always @(posedge clk) dpii_call();
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endmodule
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module sub_1 (
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input clk
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); /*verilator hier_block*/
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always @(posedge clk) dpii_call();
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endmodule
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