35 lines
829 B
Systemverilog
35 lines
829 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2023 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module a;
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import "DPI-C" task dpii_twice; // Legal
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export "DPI-C" task dpix_twice; // Bad
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task dpix_twice(input int i, output [2:0] o);
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o = ~i;
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endtask
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initial dpii_twice();
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endmodule
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module b;
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import "DPI-C" task dpii_twice; // Legal
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export "DPI-C" task dpix_twice; // Bad
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task dpix_twice(input int i, output [63:0] o);
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o = ~i;
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endtask
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initial dpii_twice();
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endmodule
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module t;
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a a ();
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b b ();
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initial begin
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$stop;
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end
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endmodule
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