51 lines
1.3 KiB
Systemverilog
51 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer i;
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integer count = 'd0;
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always @(posedge clk) begin
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count <= count + 1;
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if (count == 10) begin
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for (i = 0; i < 30; i = i + 4) begin
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// See issue #4480, verilator may inline getb() which has another display inside it
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$display("%d: %02x%02x%02x%02x", i, getb(i + 3), getb(i + 2), getb(i + 1), getb(i));
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end
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end
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if (count == 11) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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localparam SIZE = 64 * 1024;
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localparam ADDRW = $clog2(SIZE / 4);
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reg [31:0] ram[(SIZE/4)-1:0];
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function [7:0] getb;
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input [31:0] address;
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if (address[31:ADDRW+2] != 0) begin
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$display("Address out of range");
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end
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case (address[1:0])
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0: getb = ram[address[ADDRW+1:2]][8*0+7:8*0];
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1: getb = ram[address[ADDRW+1:2]][8*1+7:8*1];
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2: getb = ram[address[ADDRW+1:2]][8*2+7:8*2];
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3: getb = ram[address[ADDRW+1:2]][8*3+7:8*3];
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endcase
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endfunction
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initial begin
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for (i = 0; i < SIZE / 4; i = i + 1) begin
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ram[i] = {i[15:0], 16'hdead};
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end
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end
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endmodule
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