48 lines
1.0 KiB
Systemverilog
48 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t;
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logic clk = 0;
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always #5 clk = ~clk;
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initial begin
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#300;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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localparam int N = 8;
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logic [N-1:0][7:0] i = '0;
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logic [N-1:0][7:0] o;
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always @(posedge clk) begin
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for (int n = 0; n < N; ++n) begin
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i[n] <= i[n] + 8'(n);
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end
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end
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for (genvar n = 0; n < N; ++n) begin
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assign o[n] = ~i[n];
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end
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always @(posedge clk) begin
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$write("%05t i == '{", $time);
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for (int n = 0; n < N; ++n) begin
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if (n > 0) $write(", ");
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$write("%2d: %4d", n, o[n]);
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end
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$write("}\n");
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end
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endmodule
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