13 lines
293 B
Systemverilog
13 lines
293 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Geza Lore
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// SPDX-License-Identifier: CC0-1.0
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module top(
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input wire [1:0] i,
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output wire [3:0] o
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);
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assign o = 4'd2 ** i;
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endmodule
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