16 lines
402 B
Systemverilog
16 lines
402 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for issue #3817
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// addDriver() was causing use-after-free and segfaulting during Verilation
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Jevin Sweval
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// SPDX-License-Identifier: CC0-1.0
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module t (
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output [2:0] c_b_a,
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input a,
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input b,
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input c
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);
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assign c_b_a = {c, {b, a}};
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endmodule
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