80 lines
1.7 KiB
Systemverilog
80 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module M0 #(parameter PRMTR = 1) (
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output int value
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);
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assign value = PRMTR;
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endmodule
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module M1 #(parameter PRMTR = 1)(
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output int value
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);
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int v0, v1;
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M0 m0a (.value(v0));
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M0 m0b (.value(v1));
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assign value = v0 + v1;
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endmodule
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module M2 #(parameter PRMTR = 1)(
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output int value
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);
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M1 m1 (.value(value));
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endmodule
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module M3 #(parameter PRMTR = 1)(
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output int value
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);
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int v0, v1;
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M2 m2a (.value(v0));
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M2 m2b (.value(v1));
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assign value = v0 * v1;
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endmodule
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module top;
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int value;
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M3 m3 (.value(value));
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defparam m3.m2a.m1.m0a.PRMTR = 2;
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defparam m3.m2a.m1.m0b.PRMTR = 3;
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defparam m3.m2b.m1.m0a.PRMTR = 4;
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defparam m3.m2b.m1.m0b.PRMTR = 5;
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defparam m3.m2a.m1.PRMTR = 6;
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defparam m3.m2b.m1.PRMTR = 7;
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defparam m3.m2a.PRMTR = 8;
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defparam m3.m2b.PRMTR = 9;
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defparam m3.PRMTR = 10;
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initial begin
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`checkh(m3.m2a.m1.m0a.PRMTR, 2);
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`checkh(m3.m2a.m1.m0b.PRMTR, 3);
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`checkh(m3.m2b.m1.m0a.PRMTR, 4);
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`checkh(m3.m2b.m1.m0b.PRMTR, 5);
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`checkh(m3.m2a.m1.PRMTR, 6);
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`checkh(m3.m2b.m1.PRMTR, 7);
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`checkh(m3.m2a.PRMTR, 8);
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`checkh(m3.m2b.PRMTR, 9);
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`checkh(m3.PRMTR, 10);
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#1;
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`checkh(value, 45); // (2+3) * (4+5)
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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