50 lines
1.1 KiB
Systemverilog
50 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Test transition bins - simple two-value transitions
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic [2:0] state;
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covergroup cg;
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cp_state: coverpoint state {
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bins trans1 = (0 => 1);
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bins trans2 = (1 => 2);
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bins trans3 = (2 => 3);
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}
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endgroup
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cg cg_inst = new;
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int cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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case (cyc)
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0: state <= 0;
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1: state <= 1; // 0 => 1 (trans1 should hit)
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2: state <= 2; // 1 => 2 (trans2 should hit)
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3: state <= 3; // 2 => 3 (trans3 should hit)
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4: begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endcase
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// Sample the covergroup manually each clock
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cg_inst.sample();
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// Auto-stop after 10 cycles to prevent infinite loop
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if (cyc > 10) begin
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$display("ERROR: Test timed out");
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$stop;
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end
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end
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endmodule
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