43 lines
1.2 KiB
Systemverilog
43 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Test transition bins - 3-value sequences
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// Known limitation: multi-value (3+) transition bins generate incomplete case
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// statements; complex transitions are not fully supported.
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic [2:0] state;
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covergroup cg;
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cp_state: coverpoint state {
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bins trans_3val = (0 => 1 => 2); // 3-value sequence
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bins trans_3val_2 = (2 => 3 => 4); // Another 3-value sequence
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}
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endgroup
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cg cg_inst = new;
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initial begin
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// Test sequence 1: 0 => 1 => 2 (should complete trans_3val)
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state = 0;
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cg_inst.sample();
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state = 1; // 0 => 1 (state machine now at position 1)
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cg_inst.sample();
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state = 2; // 1 => 2 (completes trans_3val: 0=>1=>2)
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cg_inst.sample();
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// Test sequence 2: 2 => 3 => 4 (should complete trans_3val_2)
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state = 3; // 2 => 3 (state machine now at position 1 for trans_3val_2)
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cg_inst.sample();
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state = 4; // 3 => 4 (completes trans_3val_2: 2=>3=>4)
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cg_inst.sample();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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