44 lines
1.2 KiB
Systemverilog
44 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test iff (enable) guard: sampling is gated by the enable condition.
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// Samples taken while enable=0 must not increment bins.
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// Bins 'disabled_*' are sampled only with enable=0 -- they must NOT appear in
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// coverage.dat. Bins 'enabled_*' are sampled only with enable=1 -- they must
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// appear. This makes pass/fail unambiguous from the coverage report alone.
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module t;
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logic enable;
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int value;
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covergroup cg_iff;
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cp_value: coverpoint value iff (enable) {
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bins disabled_lo = {1};
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bins disabled_hi = {2};
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bins enabled_lo = {3};
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bins enabled_hi = {4};
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}
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endgroup
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cg_iff cg = new;
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initial begin
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// Sample disabled_lo and disabled_hi with enable=0 -- must not be recorded
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enable = 0;
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value = 1; cg.sample();
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value = 2; cg.sample();
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// Sample enabled_lo and enabled_hi with enable=1 -- must be recorded
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enable = 1;
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value = 3; cg.sample();
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value = 4; cg.sample();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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