46 lines
993 B
Systemverilog
46 lines
993 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module - Edge case: empty covergroup
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test: Empty covergroup (no coverpoints)
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// Expected: Should compile, coverage should be 100% (nothing to cover)
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic [7:0] value;
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// Empty covergroup - no coverpoints defined
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covergroup cg_empty;
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// Intentionally empty
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endgroup
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cg_empty cg_inst = new;
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int cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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value <= value + 1;
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cg_inst.sample();
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if (cyc == 5) begin
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real cov;
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cov = cg_inst.get_inst_coverage();
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$display("Empty covergroup coverage: %f%%", cov);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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if (cyc > 10) begin
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$display("ERROR: Test timed out");
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$stop;
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end
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end
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endmodule
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