39 lines
869 B
Systemverilog
39 lines
869 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// Test that functional coverage is properly written to coverage database
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// Checks that coverage.dat contains covergroup entries with correct format
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// Expected coverage database entries will contain:
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// - Type "covergroup"
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// - Bin names ("low", "high")
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// - Hierarchy ("cg.cp.low", "cg.cp.high")
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module t (/*AUTOARG*/);
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logic [1:0] data;
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covergroup cg;
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cp: coverpoint data {
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bins low = {2'b00};
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bins high = {2'b11};
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}
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endgroup
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cg cg_inst = new;
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initial begin
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// Sample both bins
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data = 2'b00;
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cg_inst.sample();
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data = 2'b11;
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cg_inst.sample();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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