57 lines
1.1 KiB
Systemverilog
57 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test small cross coverage with inline implementation
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc = 0;
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logic [3:0] a;
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logic [3:0] b;
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covergroup cg @(posedge clk);
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option.per_instance = 1;
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// 2-way cross: 44 = 16 bins (< 64 threshold, should use inline)
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cp_a: coverpoint a {
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bins a0 = {0,1,2,3};
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bins a1 = {4,5,6,7};
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bins a2 = {8,9,10,11};
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bins a3 = {12,13,14,15};
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}
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cp_b: coverpoint b {
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bins b0 = {0,1,2,3};
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bins b1 = {4,5,6,7};
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bins b2 = {8,9,10,11};
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bins b3 = {12,13,14,15};
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}
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cross_ab: cross cp_a, cp_b;
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endgroup
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cg cg_inst = new;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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a <= cyc[3:0];
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b <= cyc[7:4];
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if (cyc == 20) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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