46 lines
1.0 KiB
Systemverilog
46 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Test covergroup clocked (automatic) sampling
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// Tests --no-timing (default) mode; see t_covergroup_auto_sample_timing for --timing variant.
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic [1:0] data;
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// Covergroup with automatic sampling on posedge clk
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covergroup cg @(posedge clk);
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cp_data: coverpoint data {
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bins zero = {2'b00};
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bins one = {2'b01};
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bins two = {2'b10};
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bins three = {2'b11};
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}
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endgroup
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cg cg_inst = new;
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int cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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case (cyc)
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0: data <= 2'b00;
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1: data <= 2'b01;
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2: data <= 2'b10;
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3: data <= 2'b11;
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4: begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endcase
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// NOTE: NO manual .sample() call - relying on automatic sampling!
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end
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endmodule
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