43 lines
970 B
Systemverilog
43 lines
970 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test implicit auto-bin creation (no explicit bins) and option.auto_bin_max
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module t;
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logic [2:0] data3;
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// Test 1: auto_bin_max default (64) - creates 8 bins for 3-bit signal
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covergroup cg1;
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cp_data3: coverpoint data3;
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endgroup
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// Test 2: auto_bin_max = 4 - creates 4 bins: [0:1],[2:3],[4:5],[6:7]
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covergroup cg2;
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option.auto_bin_max = 4;
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cp_data3: coverpoint data3;
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endgroup
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initial begin
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cg1 cg1_inst;
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cg2 cg2_inst;
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cg1_inst = new;
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cg2_inst = new;
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data3 = 0; cg1_inst.sample();
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data3 = 3; cg1_inst.sample();
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data3 = 0; cg2_inst.sample();
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data3 = 4; cg2_inst.sample();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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