31 lines
778 B
Systemverilog
31 lines
778 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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wire a = cyc[0];
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wire b = cyc[0];
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always @(posedge clk) begin
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cyc <= cyc + 1;
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// Before this was optimized, with --coverage-line
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// error: self-comparison always evaluates to true [-Werror=tautological-compare]
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// if (((1U & vlSelf->t__DOT__cyc) == (1U & vlSelf->t__DOT__cyc)))
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if (a != cyc[0]) $stop; // Becomes cyc == cyc after substitution
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if (b != cyc[0]) $stop;
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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