15 lines
324 B
Systemverilog
15 lines
324 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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class Cls1;
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randc int rc;
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constraint c_bad { soft rc > 4; } // Bad, no soft on randc
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endclass
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module t;
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endmodule
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