21 lines
576 B
Systemverilog
21 lines
576 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2021 Michael Lefebvre
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// SPDX-License-Identifier: CC0-1.0
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module t;
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localparam int unsigned A2[1:0] = '{5, 6};
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localparam int unsigned A3[2:0] = '{4, 5, 6};
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// Matching sizes with slicesel are okay.
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localparam int unsigned B22[1:0] = A2[1:0];
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localparam int unsigned B33[2:0] = A3[2:0];
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// See issue #3186
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localparam int unsigned B32_B[1:0] = A3[1:0];
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localparam int unsigned B32_T[1:0] = A3[2:1];
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endmodule
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