32 lines
569 B
Systemverilog
32 lines
569 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module m1;
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initial $stop;
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endmodule
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module m2;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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// not defined: module m3;
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config cfg1;
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design m1;
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endconfig : cfg1 // Test end label
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// Check --top picks this config
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config cfg2;
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design m2; // Test without library name
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endconfig
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config cfg3;
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design work.m3;
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endconfig
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