44 lines
928 B
Systemverilog
44 lines
928 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit clk = 0, foo = 0, bar = 0;
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always #5 clk = ~clk;
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clocking cb @(posedge clk);
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input #11 output #2 foo;
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inout bar;
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endclocking
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initial begin
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cb.foo <= 1;
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cb.bar <= 1;
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if (foo != 0 || cb.foo != 0) $stop;
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if (bar != 0 || cb.bar != 0) $stop;
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@(posedge bar) if ($time != 5) $stop;
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if (foo != 0 || cb.foo != 0) $stop;
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if (cb.bar != 0) $stop;
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#1 if (foo != 0 || cb.foo != 0) $stop;
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if (cb.bar == 1) $stop;
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@(posedge foo) if ($time != 7) $stop;
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if (cb.foo != 0) $stop;
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#9 // $time == 16
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if (cb.foo != 0)
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$stop;
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#10 // $time == 26
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if (cb.foo != 1)
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$stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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