92 lines
2.1 KiB
Systemverilog
92 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Check initialisation of cloned clock variables
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//
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// This tests issue #1327 (Strange initialization behavior with
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// "VinpClk" cloned clock variables)
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2018 Rupert Swarbrick (Argon Design)
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// SPDX-License-Identifier: CC0-1.0
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// bug1327
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// This models some device under test with an asynchronous reset pin
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// which counts to 15.
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module dut (
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input wire clk,
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input wire rst_n,
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output wire done
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);
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reg [3:0] counter;
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always @(posedge clk or negedge rst_n) begin
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if (rst_n & !clk) begin
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$display(
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"[%0t] %%Error: Oh dear! 'always @(posedge clk or negedge rst_n)' block triggered with clk=%0d, rst_n=%0d.",
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$time, clk, rst_n);
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$stop;
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end
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if (!rst_n) begin
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counter <= 4'd0;
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end
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else begin
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counter <= counter < 4'd15 ? counter + 4'd1 : counter;
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end
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end
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assign done = rst_n & (counter == 4'd15);
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endmodule
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module t (
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input wire clk,
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input wire rst_n
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);
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wire dut_done;
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// A small FSM for driving the test
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//
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// This is just designed to be enough to force Verilator to make a
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// "VinpClk" variant of dut_rst_n.
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// Possible states:
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//
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// 0: Device in reset
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// 1: Device running
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// 2: Device finished
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reg [1:0] state;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= 0;
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end
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else begin
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if (state == 2'd0) begin
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// One clock after resetting the device, we switch to running
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// it.
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state <= 2'd1;
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end
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else if (state == 2'd1) begin
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// If the device is running, we switch to finished when its
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// done signal goes high.
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state <= dut_done ? 2'd2 : 2'd1;
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end
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else begin
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// If the dut has finished, the test is done.
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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wire dut_rst_n = rst_n & (state != 0);
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wire done;
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dut dut_i (
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.clk(clk),
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.rst_n(dut_rst_n),
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.done(dut_done)
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);
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endmodule
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