101 lines
1.7 KiB
Systemverilog
101 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2017 Todd Strader
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// SPDX-License-Identifier: CC0-1.0
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module some_module (
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input [3:0] i_clks
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);
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logic [1 : 0] some_state;
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logic [1:0] some_other_state;
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logic the_clk;
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assign the_clk = i_clks[3];
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always @(posedge the_clk) begin
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case (some_state)
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2'b11: if (some_other_state == 0) some_state <= 2'b00;
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default: $display("This is a display statement");
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endcase
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if (the_clk) some_other_state <= 0;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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`define BROKEN
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module t1 (
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input [3:0] i_clks,
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input i_clk0,
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input i_clk1
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);
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some_module some_module (.i_clks(i_clks));
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endmodule
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module ident (
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input i_ident,
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output o_ident
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);
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assign o_ident = i_ident;
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endmodule
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module t2 (
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input [2:0] i_clks,
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input i_clk0,
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input i_clk1,
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input i_clk2,
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input i_data
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);
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logic [3:0] the_clks;
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logic data_q;
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logic ident_clk1;
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always @(posedge i_clk0) begin
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data_q <= i_data;
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end
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ident ident (
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.i_ident(i_clk1),
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.o_ident(ident_clk1)
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);
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t1 t1 (
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.i_clks({ident_clk1, i_clk2, ident_clk1, i_clk0}),
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.i_clk0(i_clk0),
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.i_clk1(i_clk1)
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);
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endmodule
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module t (
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/*AUTOARG*/
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// Inputs
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clk /*verilator clocker*/ /*verilator public_flat*/,
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input clk0 /*verilator clocker*/,
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input clk1 /*verilator clocker*/,
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input clk2 /*verilator clocker*/,
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input data_in
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);
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input clk;
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logic [2:0] clks;
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assign clks = {1'b0, clk1, clk0};
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t2 t2 (
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.i_clks(clks),
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.i_clk0(clk0),
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.i_clk1(clk),
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.i_clk2(clk2),
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.i_data(data_in)
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);
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endmodule
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