30 lines
589 B
Systemverilog
30 lines
589 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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class Base;
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int j;
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function new(int x);
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j = x;
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endfunction
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static function int get_default();
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return 8;
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endfunction
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endclass
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class Derived extends Base;
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function new();
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super.new(get_default());
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endfunction
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endclass
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module t;
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initial begin
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automatic Derived d = new;
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if (d.j != 8) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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