42 lines
766 B
Systemverilog
42 lines
766 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2011 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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// verilog_format: off
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always @(*) begin
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if (clk) begin end
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end
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always @(* ) begin
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if (clk) begin end
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end
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// Not legal in some simulators, legal in others
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// always @(* /*cmt*/ ) begin
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// if (clk) begin end
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// end
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// Not legal in some simulators, legal in others
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// always @(* // cmt
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// ) begin
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// if (clk) begin end
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// end
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always @ (*
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) begin
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if (clk) begin end
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end
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// verilog_format: on
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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