35 lines
558 B
Systemverilog
35 lines
558 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit valid;
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bit clk;
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logic [7:0] out;
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logic [7:0] in;
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initial begin
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valid = 1;
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out = 2;
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in = 2;
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end
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property prop;
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@(posedge clk) (valid) |-> ##2 (out == in + 3);
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endproperty
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assert property (prop);
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initial begin
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forever begin
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#(10) clk = ~clk;
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end
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end
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initial #200 $finish;
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endmodule
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