verilator/test_regress/t/t_assert_procedural_clk_bad...

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%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:19:9: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6)
: ... note: In instance 't'
19 | assume property (@(posedge clk) cyc == 9);
| ^~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:20:9: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6)
: ... note: In instance 't'
20 | assume property (@(negedge clk) cyc == 9);
| ^~~~~~
%Error: Exiting due to