68 lines
2.1 KiB
Systemverilog
68 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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int cyc;
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reg [63:0] crc;
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// Derive signals from non-adjacent CRC bits (lesson 17: avoid shift correlation)
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wire a = crc[0];
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wire b = crc[4];
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wire c = crc[8];
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wire d = crc[12];
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int count_fail1 = 0;
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int count_fail2 = 0;
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int count_fail3 = 0;
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int count_fail4 = 0;
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// Test 1: a[->2] |-> b (overlapping implication, 2 non-consecutive occurrences)
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assert property (@(posedge clk) a[->2] |-> b)
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else count_fail1 <= count_fail1 + 1;
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// Test 2: a[->1] |-> c (single occurrence, overlapping)
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assert property (@(posedge clk) a[->1] |-> c)
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else count_fail2 <= count_fail2 + 1;
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// Test 3: a[->3] |=> d (3 occurrences, non-overlapping implication)
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assert property (@(posedge clk) a[->3] |=> d)
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else count_fail3 <= count_fail3 + 1;
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// Test 4: standalone goto rep (no implication) -- exercises standalone visitor
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assert property (@(posedge clk) b[->2])
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else count_fail4 <= count_fail4 + 1;
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n",
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$time, cyc, crc, a, b, c, d);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc == 0) begin
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc == 99) begin
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`checkh(crc, 64'hc77bb9b3784ea091);
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`checkd(count_fail1, 20);
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`checkd(count_fail2, 40);
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`checkd(count_fail3, 19);
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`checkd(count_fail4, 0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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