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61 lines
1.6 KiB
Systemverilog
61 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// Ref. to IEEE 1800-2023 11.4.14
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//
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// Streaming an unpacked array whose element is an unpacked struct. The left
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// stream ({<<{}}) read used to crash V3EmitC: V3Const packed the aggregate
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// source but then re-wrapped the now-packed expression in AstCvtArrayToPacked,
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// which EmitC dereferenced as an array.
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module t( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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`define checkh(gotv, expv) \
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do if ((gotv) !== (expv)) begin \
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$write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__, `__LINE__, (gotv), (expv)); \
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$stop; \
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end while (0);
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typedef struct {
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logic [7:0] a;
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logic [7:0] b;
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} s_t;
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typedef s_t arr_t[2]; // unpacked array of unpacked struct
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localparam int W = $bits(arr_t);
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integer cyc = 0;
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reg [63:0] crc = 64'h5aef0c8d_d70a4497;
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wire [W-1:0] src = crc[W-1:0];
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arr_t aw_r, aw_l;
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always_comb {>>{aw_r}} = src;
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always_comb {<<8{aw_l}} = src;
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wire [W-1:0] rd_r = {>>{aw_r}};
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wire [W-1:0] rd_l = {<<8{aw_l}}; // {<<{}} read of aggregate array previously crashed
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always @(posedge clk) begin
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc > 1) begin
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`checkh(rd_r, src);
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`checkh(rd_l, src);
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end
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if (cyc == 20) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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